1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method, wiring and a semiconductor device and, more particularly, to a semiconductor device manufacturing method, wiring and a semiconductor device using polycrystalline silicon (Si) or polycrystalline silicon germanium (SiGe) as a gate electrode material.
2. Background Art
In recent years, large-scale integrated circuits (LSIs) formed by coupling a multiplicity of components including transistors and resistors to each other in an electrical circuit and by integrating the components into one chip have been put to greater use in important portions of computers and communication apparatuses. Therefore the overall performance of such apparatuses depends largely on the performance of LSIs in a single state.
An improvement in performance of an LSI in a single state can be achieved, for example, by increasing the degree of integration, i.e., by making elements smaller. An element, e.g., a MOS field effect transistor (MOS FET) can be made smaller by reducing the gate length and reducing the thickness of source and drain regions.
As a method for forming shallow source and drain regions, a low-speed ion implantation method is being widely used. This method ensures that source and drain regions having a depth of 0.1 μm or smaller can be formed.
An impurity diffusion layer formed by the low-speed ion implantation method, however, has a high sheet resistance of 100Ω/□ or more. An increase in operating speed by the smaller elements cannot be expected if this problem is not solved.
In a device such as a logic LSI of which high-speed operation is required, a silicide film is formed on the surfaces of a source diffusion layer, a drain diffusion layer and a gate electrode (n+ or p+ polycrystalline silicon) in a self-alignment manner, that is, salicide (self-aligned silicide) is used in order to reduce the resistance of the source, drain and gate.
In a case where a dual gate structure using n+ and p+ polycrystalline silicon as a base for a silicide layer in the same layer is adopted, a salicide structure is effective in simplifying the process as well as in reducing the resistance of a gate electrode. This is because, when a source and a drain are doped with an impurity, doping of gate polycrystalline silicon can be simultaneously performed. In general, a salicide process is a technique to form silicide only on a source, a drain, a gate electrode and wiring Si in a self-alignment manner by forming a metal film on Si and an insulating film pattern and heating the metal film. In some case, a PMOS FET and an NMOS FET are formed side by side.
In a case where a PMOS FET and an NMOS FET are formed side by side, a region doped simultaneously with two kinds of impurities: n-type and p-type impurities exists in a semiconductor layer. If a salicide process is performed on this region, various problems relating to the silicide layer formed by the process arise, depending on a combination of used materials, a temperature condition. In such a case, the silicide layer cannot be uniformly formed and a low-resistance electrode and a low-resistance wiring structure cannot be obtained.